MEO Satellite Payload Engineer
il y a 1 semaine
Location:
Luxembourg
Security Clearance:
EU Secret
Reference No:
VS/SES-02 / Luxembourg
Education/Experience
- Master's degree or Ph.D. in electrical engineering, computer engineering, or a similar discipline.
- 10+ years of electronic equipment design experience, preferably in the space sector.
- Hands-on experience in implementing FPGA, RF SoC, ASIC and processor-based designs.
- Fluency in English; any other language considered an asset.
- Willingness to work at least 66% onsite and to travel as required for project realisation purposes.
Desirable Skills
- Working independently in complex, multi-stakeholder environments and demonstrating flexibility and adaptability.
- Thinking strategically, solving problems effectively and making sound decisions; communicating clearly in writing and verbally.
- Exercising strong leadership with proven project and team management skills; proficiency with project management tools and methodologies.
- Defining high-level requirements; identifying key industrial and technology partners; integrating third-party IP.
- Understanding full digital electronic equipment and IC design flows (from architecture and RTL to PCB/GDSII).
- Applying digital signal processing theory and practice; designing high-speed DSP blocks across multi-power and multi-clock domains.
- Using EDA tools for electronic design (e.g., Altium Designer) and working with Mixed-Signal ICs (ADCs/DACs, modems, channelisers, beamforming) and high-/low-speed interfaces (JESD204C, PCIe, Ethernet; CAN, SPI, I2C, RS-422/485).
- Being familiar with software-defined design procedures, functional and timing analysis in DSP contexts; 4G/5G/DVB-S2X PHY/MAC; and network-layer concepts (MPLS, VPNs, TCP/UDP, L2/L3 switches, VLANs).
- Following space-industry best practices for design, verification, test, and deployment; mitigating radiation effects; addressing thermal and mechanical constraints.
- Performing reliability analyses (worst case, failure propagation, parts stress/derating, end-of-life) and selecting space EEE parts for reliability, screening, and anti-counterfeit.
Duties
- Leading the definition of requirements and documentation for all digital hardware (ASICs, boards, equipment) and submodules.
- Identifying and mastering FPGA/SoC/Processor/ASIC architectures for onboard regenerative processing, digitally beamformed active antennas, and ground user terminals.
- Performing exhaustive exploration of architectural implementations, analysing trade-offs, and evaluating key performance metrics (signal integrity, service quality, power, thermal behaviour, cost, system limitations).
- Defining subsystem architectures and verification methodologies; producing and maintaining architecture-level documentation to enable downstream design activities.
- Defining technical specifications for digital subsystems in coordination with internal stakeholders and external industrial partners.
- Reviewing and coordinating electronic, physical, mechanical, and thermal design processes; providing hands-on support to stakeholders as needed.
- Defining, reviewing, and coordinating risk mitigation activities, including testing prototype models in the lab and supporting in-orbit demonstration.
- Providing performance-metrics support to payload and user terminal stakeholders and higher-assembly-level design and analysis; collaborating with cross-functional teams.
- Documenting digital subsystem design specifications, analyses, test plans, and verification reports.
- Collaborating with internal stakeholders and partners throughout the subsystems' life cycle.
Additional information:
If you are interested, for further information, please contact the point of contact for this offer.
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