Senior HDL Designer

Il y a 3 mois

Luxembourg LUXUAV Temps plein

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IUOQAGAYUKQ Apply for this position and join us in building Europe’s next generation infrastructure. Our values are rooted in responsibility, readiness, and long term thinking. We believe sovereignty must be designed into systems from the start. Readiness is achieved through capability, not procurement. Autonomy is infrastructure, not a feature. We build with the understanding that modern systems carry long term consequences. That is why we prioritise reliability over novelty, integration over isolation, and sustained capability over short term advantage. Apply for this position Position Role Overview This engineering position is focused on designing FPGA configurations for fast image processing, real-time process control, and SDR (Software Defined Radio) systems. The role involves translating system-level requirements into RTL design, developing and optimizing FPGA implementations, and collaborating closely with hardware and software engineers to deliver integrated system solutions. ‍

Key Responsibilities
• Translate system-level requirements into RTL design-level specifications.
• Analyze requirements to determine system resources, performance targets, and select appropriate FPGA devices to meet design goals.
• Develop RTL code and corresponding test benches for design modules using SystemVerilog and/or VHDL.
• Synthesize FPGA designs on physical prototypes and optimize placement and routing to achieve timing closure.
• Optimize designs with respect to technological capabilities, cost, and performance.
• Take full ownership of FPGA development and collaborate closely with hardware and software engineers to deliver integrated system-level products.
• Use laboratory equipment such as logic analyzers and oscilloscopes to debug physical prototypes alongside hardware designers. ‍ Experience & Skills Required Qualifications & Experience
• Bachelor’s or Master’s degree in Electronic Engineering, with a focus on digital, mixed-signal circuits, or power electronics design.
• Minimum 5 years of experience reading schematics and integrating FPGA designs into digital and mixedsignal electronic systems.
• Strong expertise in SystemVerilog and/or VHDL (preferably SystemVerilog). Strong expertise in digital interface protocols, including AXI-family, SPI, and PCIe.
• Experience developing signal processing algorithms such as FIR and IIR filters for RF, video, or other digital signals.
• Experience using logic analyzers, integrated logic analyzers (ILA), oscilloscopes, and other laboratory testing instrumentation.
• Good knowledge and hands-on experience with version control systems (Git).
• Ability to debug mockups and prototypes alongside electronic engineers.
• Ability to collaborate effectively within diverse engineering teams to achieve system-level design goals.
• National from a NATO member country or one of the following NATO Indo-Pacific partners: Australia, Japan, South Korea, New Zealand, or Ukraine, or NATO Clearance
• Free criminal record ‍ Preferred Qualifications & Experience
• Good knowledge of Software Defined Radio (SDR) principles and architectures.
• Familiarity with scripting languages such as Python for automating verification, testing, and laboratory workflows. ‍

Senior HDL Designer

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